NASDAQ: GSIT

discovery, and cybersecurity. Together, these capabilities enable multi-workload processing within size, weight, and power constrained environments. Revenue from our APU line has not been material to date.

We remain committed to our established synchronous SRAM business, which generates revenue that supports our APU development. We offer what we believe is the broadest portfolio of high-density, high-performance synchronous SRAM products in the market. These products are used in test and measurement equipment, high-performance networking and telecommunications infrastructure, and military/defense and aerospace applications. We maintain long-term relationships with leading original equipment manufacturer (“OEM”) customers, including KYEC, Cadence Design Systems, and Nokia. In addition, we serve the military/defense and aerospace markets with radiation-tolerant and radiation-hardened space-grade SRAMs, as well as APU-based solutions for applications such as SAR image processing.

We operate under a fabless business model, outsourcing wafer fabrication, assembly, and testing. This model allows us to focus our resources on research and development, product design, and marketing while gaining access to advanced process technologies with modest capital investment and fixed costs.

GSI’s fiscal year 2026 net revenue increased by 22% compared to net revenue in fiscal year 2025, reflecting strong SRAM sales to chip design and simulation customers. GSI’s gross margin increased by 5% compared to the prior fiscal year primarily reflecting a favorable mix weighted toward higher-margin SRAM products.

We have been awarded four contracts under the U.S. Department of Defense Small Business Innovation Research (“SBIR”) program to develop and demonstrate applications of our APU compute-in-memory architecture for military and space customers. All milestones under these contracts were completed as of March 31, 2026, except for certain amended milestones under the Space Development Agency agreement described below and the US Army xTECH agreement described below. Aggregate payments received under these contracts totaled approximately $557,000 and $1.6 million in fiscal 2025 and 2026, respectively. While these contracts validated the performance of our APU architecture in defense applications, they have not yet resulted in follow-on production contracts or material commercial revenues from the underlying technology.

Space Development Agency — SBIR Direct to Phase II (Prototype Agreement) — $2.0 million.

Development of next-generation APU2 compute-in-memory integrated circuit for space-based edge processing, including radiation-hardened capability assessment. The agreement was originally valued at $1.25 million and was amended in September 2025 to increase the total award to $2.0 million. All original milestones were completed as of March 31, 2026. Milestone payments of $435,000, $318,000, and $496,000 were received in fiscal 2024, 2025, and 2026, respectively.

AFWERX / U.S. Air Force Research Laboratory (“AFRL”) — SBIR Direct to Phase II — $1.1 million.

Development and demonstration of high-data computation use cases using the Gemini APU for AFRL, including in-aircraft search and rescue, object detection, moving target indication, change detection, and GPS-denied navigation. All milestones were completed as of March 31, 2026. Milestone payments of $157,000 and $983,000 were received in fiscal 2025 and 2026, respectively.

U.S. Army (DoD SBIR) — SBIR Phase II — Up to $250,000.

Development of edge computing AI solutions using Gemini-II, including feasibility assessment of integrating 1-bit Large Language Models for low-power, low-latency military applications. All milestones were completed as of March 31, 2026. Milestone payments of $82,000 and $165,000 were received in fiscal 2025 and 2026, respectively.

U.S. Army — xTech SBIR Phase II — $2.0 million.

Development of a ruggedized edge-processing platform based on the Gemini-II APU, with testing in representative operational environments intended to validate performance across real-time AI workloads, such as sensor data processing, object detection, and command-and-control analytics. This SBIR was awarded to GSI in April 2026.

In addition to the four SBIR’s discussed above, in January 2026, we announced a new proof-of-concept (“POC”) engagement with two government agencies. GSI is partnering with G2 Tech, an Israel Deep tech AI company, on Sentinel, a program to develop an autonomous perimeter security system that manages drones and cameras in real time for advanced monitoring, detection, and response. The project is jointly backed by the U.S. Department of War (“DoW”), formerly known as the Department of Defense (“DoD”), and a foreign government agency.

In May 2026, we announced that we were awarded Phase I of a Smart City project by a local government agency in Taiwan. The completion of Phase I will mark our first smart city deployment of the Gemini-II APU.

Our APU technology is implemented in the Gemini series of AI chips. The Gemini-I part is in full production, and the Gemini-II device is in pre-production and already in the market with sales delivery of PCIe boards and chips. There have not been substantial sales of Gemini-I parts to date. We support customers with prebuilt application program interfaces (“APIs”) and libraries to support the parallel processing capabilities of the Gemini-I and Gemini-II parts. The software stack accelerates development by providing an integrated framework environment for the compute-in-memory as well as host and management code modules. Our compiler stack framework allows customers to optimize their applications by editing APIs provided by GSI, or write their own APIs. Benchmarking on the Gemini-II has shown an industry leading capability on time-to-first-token which is being used to provide situational awareness for physical edge AI products.

In March 2025, we secured an initial production order for our radiation-hardened SRAM from a North American prime contractor, with follow-on orders expected in fiscal 2027. This sale carries a significantly higher gross margin than our traditional SRAM chips. In parallel, we are actively pursuing heritage status for this chip, which will improve our market readiness and open important new sales channels.

We were incorporated in California in 1995 under the name Giga Semiconductor, Inc. We changed our name to GSI Technology in December 2003 and reincorporated in Delaware in June 2004 under the name GSI Technology, Inc. Our principal executive offices are located at 1213 Elko Drive, Sunnyvale, California, 94089, and our telephone number is (408) 331-8800.

Recent Developments

On October 21, 2025, we entered into a securities purchase agreement (the “Purchase Agreement”) with an investor (the “Purchaser”) pursuant to which we agreed to issue and sell, in a registered direct offering (the “Registered Direct Offering”) an aggregate of (i) 1,508,462 shares (the “Shares”) of our common stock, $0.001 par value per share (the “Common Stock” or the “common stock”) at a price of $10.00 per Share and (ii) pre-funded warrants to purchase 3,491,538 shares of Common Stock (the “Pre-Funded Warrants”). Each of the Pre-Funded Warrants is exercisable for one share of Common Stock at the exercise price of $0.01 per Pre-Funded Warrant, immediately exercisable, and may be exercised at any time. The Purchaser’s ability to exercise its Pre-Funded Warrants in exchange for shares of Common Stock is subject to certain beneficial ownership limitations set forth therein. The gross proceeds to us from the Registered Direct Offering were approximately $50 million, before deducting offering expenses payable of approximately $3.1 million. The Registered Direct Offering closed on October 22, 2025. All of the Pre-Funded Warrants were exercised in October 2025.

Industry and Market Strategy

Associative Processing Unit Computing Market Overview

The markets for associative processing computing solutions are significant and growing rapidly. These markets include embedded physical AI edge products, on-premises small-medium business servers, and remote servers. The total addressable market for APU in AI, search applications, and HPC which is where GSI is focusing its APU commercialization efforts, has been determined by GSI to be approximately $247 billion in 2025, and growing at a compound annual growth rate (“CAGR”) of 27% to $708 billion by 2028. GSI has similarly determined that the Serviceable Available Market for APU in edge AI deployments in those markets is approximately $7 billion in 2025, and anticipated to grow at a CAGR of 18%-22% to $16 billion by 2030.

The growth in demand for associative processing computing solutions is being driven by the increasing market adoption and usage of graphics processing unit (“GPU”) and central processing unit (“CPU”) farms for AI processing of large data collections, including parallel computing in scientific research. However, the large-scale usage of GPU and CPU farms for AI processing of data is demonstrating the limits of GPU and CPU processing speeds and resulting in ever higher energy consumption. The amounts of data being processed, which is coming from increasing numbers of users and continuously increasing amounts of collected data, has resulted in efforts to split and store the processed data among multiple databases, through a process called sharding. Sharding can substantially increase processing costs and worsen the power consumption factors associated with processing so much data if the underlying architecture is inefficient to begin with.

The APU has been demonstrated to outperform CPUs and GPUs in the market for AI search of large data collections by providing lower latency and increased capacity in a smaller form-factor and achieve such results with lower power consumption. In addition, our compute-in-place technology has wide application. The APU has several benefits that are particularly useful to overcome the high power challenges of GPUs. First, the APU does not have the word size limitation of traditional CPU and GPU processors. Because traditional data processors move data around to various parts of a system, they need to select or duplicate resources of particular word sizes, be they 8-bit, 16-bit, 32-bit or 64-bit. The APU is based on a memory line structure, which means that it can operate on legacy instruction widths of 8 or 16-bits, or just as seamlessly operate on instructions of arbitrary widths of 1 bit, 768-bits or 2048-bits. APUs can operate on any word width at interim processing steps. This dynamic flexibility is a tremendous advantage for non-linear processing used in high performance compute workloads. Second, the APU is also an associative machine, which means that data that is resident in the device can be applied to a function only if it is deemed associated (for example, with a meta-tag) to the processing. Such processing is like a person looking for his car in a parking lot, but ignoring all cars that are not the color of his car. An additional benefit of the Gemini APU designs is that they are multi-threaded. One sensor or query input can be simultaneously applied to multiple

functions or searches in the device or to sequential different functions on a single device towards a single edge solution.

Our associative computing technology utilizes in-memory associative processor structures to address the bottlenecks that limit performance and increase power consumption in CPUs, GPUs, and Field Programmable Gate Arrays (“FPGAs”). By constantly having to move operands and results in and out of devices with ever increasing processing speeds and bus speeds, current solutions are focused on memory transfers rather than addressing the basic computation problem. By changing the computational framework to parallel processing and having search functions conducted directly in a processing memory array, the APU can greatly expedite computation and response times in many “big data” applications. We are creating a new category of computing products that are expected to have substantial target markets and a large new customer base in those markets. We are seeing adoption of this direction in research by at least one hyperscaler and by researchers. Being on our second generation device and architecting our third generation device puts us in a strong position to address target markets as the methodology becomes more mainstream.

Our commercialization efforts for the APU product are focused on markets where the APU shows factors of improvement against CPU or GPU systems. The APU differentiates itself most for similarity search, multi-modal vector search, real-time very large database search, and several scientific high-performance computing-workloads processing sensor data. The APU’s improved performance over CPU or GPU systems provides a paradigm-shifting ability to process data in real-time. As a result, we see applications for the APU in artificial intelligence applications, including approximate nearest neighbor searches, cryptography, and synthetic aperture radar as well as other fields whose processing can benefit from the APU’s smaller footprint, superior productivity, and low system power consumption. GSI has solutions to accelerate multimodal vector search as an on-prem or SaaS solution for OpenSearch and general Fast Vector Search, and for processing large area SAR images in real-time at high resolution.

Similarity search uses a technique called distance metric learning, in which learning algorithms measure how similar related objects are to each other. The APU is well suited for very fast similarity search because its design determines distance metric at fast computation speeds with high degrees of accuracy. Our APU is further differentiated from other solutions in the market by its scalability for very large datasets. The APU has demonstrated its ability to increase the rate of computation for visual search by orders of magnitude with greater accuracy and reduced power consumption. The APU also adds multi-modal search capability to this computational performance. For instance, the ability to search on a picture of a product on an ecommerce website, with pricing and specific filters, does not impede the performance of the in-memory search versus a traditional text only search. This kind of performance has the potential to transform online retailers’ capabilities to run search queries and improve customers’ online shopping experience.

As we continue our efforts to simplify use of the Gemini devices in the markets discussed, we also see opportunities in the edge applications of these markets. In the edge segment the high power and small database coverage of single GPUs is not suitable. While some edge products are coming to market, they do not have the capacity to provide large database support. The APU capabilities and the larger capacity of the Gemini-II chip are well suited for this growing segment. In an attempt to address greater density in processed data, the market is working to reduce bit widths used in models. As the APU technology is ideally suited for smaller bit widths, and including even 1-bit, we are undertaking an effort to adopt several AI models to 1-bit and ternary (1.58-bit) optimization for Gemini-II application. We see this effort as furthering the density and value of our parts for the edge market.

Our commercialization efforts for the Gemini-II APU are focused on markets where low latency, deterministic response, and system efficiency provide clear advantages over conventional CPU and GPU architectures. Gemini-II extends the capabilities of the prior generation beyond high-throughput vector and

similarity search into real-time inference domains, enabling fast time-to-first-token (“TTFT”) for vision-language models (“VLMs”) and vision-language-action systems. These capabilities are increasingly critical in emerging physical AI applications, where systems must interpret sensor data and respond within operationally relevant time constraints. Gemini-II delivers these capabilities in a compact, low power form factor, enabling deployment in size, weight, and power constrained environments where traditional accelerators are impractical.

Gemini-II’s architecture is optimized for memory-resident computation, allowing large models and datasets to be processed without the memory movement latency penalties associated with GPUs. This enables rapid initial inference response, or TTFT, which is a key performance metric for interactive and autonomous systems. In contrast to conventional GPU pipelines that prioritize throughput, Gemini-II is designed to minimize inference latency at the point of decision, making it well suited for edge-deployed systems requiring real-time situational awareness and control with continuously new image data. These include robotics, autonomous platforms, industrial sensing systems, and defense applications.

The device maintains strong applicability for similarity search, multi-modal vector search, and large-scale database operations, while extending these capabilities into streaming and real-time inference workflows. For example, Gemini-II can support VLM-based interpretation of video, imagery, command and control, and sensor inputs with response times enabling systems to extract semantic meaning and act on that information in near real time. Gemini-II enables both rapid feature extraction and higher-level inference for awareness-driven decisions within constrained edge environments.

As edge systems evolve toward greater autonomy, the ability to combine low-latency inference with high data locality becomes increasingly important. Gemini-II is designed to address this requirement, enabling a new class of physical AI systems that integrate perception, reasoning, and action within tight power and latency budgets.

New Markets for the APU

The APU is capable of processing large data arrays in a cost competitive solution for large database similarity search, but the mathematical capabilities of the APU also create new opportunities in real-time processing. Examples of real-time processing are SAR, Global Positioning System (“GPS”)-denied navigation, and physical AI awareness. This combination of sensor processing, image processing, and AI awareness capability at low latency and low power has the potential to bring application processing that normally requires many resources in a data center to small form-factor real-time edge applications. Examples are in-asset aircraft reconnaissance, satellite image processing, and autonomous navigation. Awareness in physical AI has the potential of significantly improving safety and efficiency of autonomous products. It can also be used in drones for location recognition, object recognition, and GPS-denied alternate routing useful product delivery or reconnaissance applications.

Furthermore, GSI’s expertise in developing radiation-tolerant components creates new opportunities in the growing market for AI products that can be used in low earth orbit and space applications, where other AI products are not able to survive the harsh environment.

For even smaller footprints or multi-function integrated chips, GSI will license the intellectual property (“IP”) underlying the APU to companies that have their own chip design capabilities to incorporate GSI’s IP into their custom products, and provide design services to help integrate the IP into new processor, FPGA, or application specific integrated circuit (“ASIC”) designs.

Next Generation APU – Plato

The processing proven by the APU, particularly Gemini-II, has provided tremendous insights into growth capabilities via evolving workload requirements. GSI is rapidly taking advantage of this insight via the design of the next generation APU internally named Plato. The AI market at large has observed that once sufficient processing

efficiency is achieved, larger LLM workloads are less impacted by processing capability than by the ability to get data from external memory to the processing engines. This single physical limitation highly advantages the APU architecture more than CPU, GPU, or FPGA because the APU is a compute-in-memory structure that is far less encumbered by tighter and tighter path restrictions as the data approaches processing as seen in those other architectures. While competition in this area looks to solve the problem with higher power and faster communication links and high-cost HBM memory interfaces, GSI believes that increasing the external memory bandwidth capability of the APU and using LPDDR memory can balance the high capability APU compute with data transfer capabilities that will result in differentiated high performance LLM processing. This change will extend the market leading single chip time-to-first-token capability of the Gemini-II with higher ongoing token per second capability.

Plato will have a smaller resident internal model space, but more efficient low quantization capability. This will allow larger model support than competition due to efficient support of 1-bit and ternary quantization. This processing sizing is done to support sub-20W applications which will efficiently provide context awareness for autonomous mobile robotics such as humanoid robots, delivery vehicles, and drones. The power and compute capability of Plato is a good match to new processing interest shown for satellites, also extending the past application POCs of the APU into fielded programs. Such a small SWaP footprint also enables local remote processing at curb-edge facilities for networking and new applications such as V2X in ADAS fielding operations. Simple scaling capability without the need to add high power communications links also supports larger server card builds. The markets noted above together represent a TAM of several tens of billions of dollars, and while Gemini-II addresses these markets it is anticipated that Plato will increase addressable sales and open new avenues in the migration of AI to the autonomous edge.

While GPU’s and FPGA’s are less efficient for high performance edge applications for reasons noted earlier, there are a number of custom ASICs being designed and discussed in the market. Plato will be differentiated from these custom solutions along two vectors even as they also come to market in the future. First, Plato is not just an implementation of a single optimized software algorithm, but a culmination of learning from earlier actual production parts. This difference alone highly reduces implementation and production scaling risk on new hardware, which frankly, is hard. The second differentiation comes from the inherent programming flexibility of the APU. This means that as models and algorithms change, sometimes quarterly, the hardware is not orphaned to an out-of-date methodology. In fact, the 1-bit support capability of the APU technology means that Plato is intrinsically capable of supporting the direction research is taking to increase model density.

APU Board Level Product

Sales of the Gemini-II have begun with the availability of a full size double width PCIe card called Leda-E2. The Gemini-II chip is available in pre-production. The Gemini-I APU is currently in production as a full-size PCIe card and a 1U E1.L card. These are the Leda-E and Leda-S, respectively.

The Leda-S E1.L form factor enables the use of market standard SSD rack enclosures to build a dense APU compute appliance unachievable by GPU cards that require specialized connectivity for expansion. GSI has off-the-shelf server product offerings with 8 Leda-E cards in a single 2U server providing 10 POPS of Boolean operation, and a single 1U server with 16 Leda-S cards providing 15 POPs of Boolean performance.

APU Commercialization Risk

Sales of APU products continue to be in the research and academic areas and our commercialization efforts proceed through proof of concept stages that take time. Revenue from APU products has not been material to date. If we fail to materially commercialize our APU products, we may not generate sufficient revenues to offset our development costs and other expenses, which will have an adverse impact on our business including a potential impairment of intangible assets and a negative impact on our market capitalization.

High-Speed Synchronous SRAM Market Overview

High-speed synchronous SRAMs are incorporated into a range of end markets, including networking and telecommunications equipment, military/defense and aerospace systems, audio/video processing, test and measurement instruments and medical and automotive applications. Demand for high-speed synchronous SRAMs in the networking and telecommunications market has been declining, and is expected to continue to decline, as the industry embeds increasing amounts of SRAM into each successive generation of ASICs and controllers, reducing the need for external memory. As a result, growth in demand for external high-speed synchronous SRAMs is increasingly driven by military/defense and aerospace applications, which require a combination of high densities and high random transaction rates. GSI is well positioned to serve these markets as the only SRAM manufacturer to offer monolithic 288Mb densities and the highest truly random transaction rate in the industry at 1,866 million transactions per second (MT/s). To capitalize on these strengths, we have been qualifying our products for space and satellite applications to address opportunities in the rapidly expanding market for near-earth orbiting satellite mega-constellations, as well as traditional geostationary earth orbit communication platforms and national assets.

High-Speed Synchronous SRAM Products

We offer four families of high-speed synchronous SRAMs – SyncBurst™, NBT™, SigmaQuad™, and SigmaDDR™. All four families feature high density, high transaction rates, high data bandwidth, low latency, and low power consumption, and together provide the basis for approximately 10,000 individual part numbers across a variety of density, data width performance, temperature, and package configurations. Our products serve a broad range of applications, including networking and telecommunications equipment, such as routers, gateways, Ethernet switches and wireless base stations, military/defense and aerospace systems such as radar, guidance systems and satellites, test and measurement instruments such as burn-in chambers and high-speed testers, high-performance computing applications such as high-volume trading, and medical devices such as ultrasound and CAT scan equipment.

We have introduced and continue to market radiation-hardened, or “RadHard”, and radiation-tolerant, or “RadTolerant”, SRAMs for military/defense and aerospace applications, including satellite networking and missile systems. Our RadHard and RadTolerant product line includes 288 megabit, 144 megabit, and 72 megabit devices from the SigmaQuad-II+ family, as well as 144 megabit, 72 megabit, and 32 megabit SyncBurst and NBT RadTolerant products designed to support the avionics and other space platforms that have historically relied on smaller asynchronous devices. RadHard products are available in two package options: a hermetically sealed ceramic column grid array, and standard plastic packaging. These devices undergo a specialized fabrication process that mitigates the adverse effects of high-radiation environments.

SRAM Leadership in the High Performance Memory Market

We seek to address the full lifecycle needs of our SRAM customers, both satisfying their current requirements for the latest generation, highest performance networking memory products and providing long-term support throughout the operational lives of the systems incorporating our products. The key elements of our SRAM solution include:

●Product Performance Leadership. We develop high-performance SRAM products that offer superior speed and low power consumption, utilizing advanced architectures, design methodologies and silicon process technologies that enable optimized yields, lower manufacturing costs and improve quality.

●Product Innovation. We believe we have established a leadership position as a technology leader in the design and development of Very Fast SRAMs. Our SigmaQuad-II + is believed to be the industry’s highest-density RadHard SRAM, exemplifying our commitment to product innovation.

●Broad and Readily Available Product Portfolio. We have what we believe is the broadest catalog of Very Fast SRAM products.

●Master Die Methodology. Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set so that we are able to maintain a common pool of wafers that incorporate all available master die, allowing rapid fulfillment of customer orders and reducing costs.

●Customer Responsiveness. We work closely with leading networking and telecommunications OEMs and their chipset suppliers to anticipate their requirements and rapidly develop solutions that enable them to meet their product performance objectives.

Business Transformation Strategy

Our objective is to market and sell transformative new products utilizing our cutting-edge in-place associative computing technology in high growth markets, while continuing to profitably increase our share of the external SRAM market. Our strategy includes the following key elements:

●Complete productization of our In-place Associative Computing products. Our principal operations objective is the completion of productization efforts for our in-place associative computing products.

●Identifying and developing new long tail markets where the APU is differentiated. Realization of this goal will require additional development and marketing efforts in calendar 2025. Our initial focus is in the markets for artificial intelligence and high-performance computing, including natural language processing, computer vision and cyber security with a focus in this area being for similarity search applications including facial recognition, drug discovery and drug toxicity, signal and object detection and cryptography.

●Identify opportunities and rapidly increase sales of RadHard and RadTolerant SRAMs. We continue to aggressively target the military/defense and aerospace markets with our RadHard and RadTolerant devices. We plan to continue expansion into the military/defense and aerospace markets with our APU platform that has shown design robustness.

●Exploit opportunities to expand the market for our SRAM products. We are continuing the expansion of sales of our high-performance SRAM products in the military, industrial, test and measurement, and medical markets and intend to continue penetrating these and other new markets with similar needs for high-performance SRAM technologies.

●Collaborate with wafer foundry to leverage advanced process technologies. We will continue to utilize complementary metal-oxide semiconductor fabrication process technologies from Taiwan Semiconductor Manufacturing Company (“TSMC”) to design our products.

●Seek new market opportunities. We intend to supplement our internal development activities by seeking additional opportunities to acquire other businesses, product lines or technologies, or enter into strategic partnerships, that would complement our current product lines, expand the breadth of our markets, enhance our technical capabilities, or otherwise provide growth opportunities.

Customers

For our compute-in-memory associative computing solutions, we are focusing sales and marketing efforts in the markets for artificial intelligence and high-performance computing, with leading applications in natural language processing, computer vision and synthetic aperture radar. Our focus in this area being for similarity search acceleration in fast vector search applications and real-time mobile applications in aerospace and defense.

With the SRAM market, we are focusing our sales on network/telecom OEMs, test equipment and military/defense and aerospace with our radiation hardened and radiation tolerant product offerings.

The following is a representative list of our OEM customers that directly or indirectly purchased more than $500,000 of our SRAM products in the fiscal year ended March 31, 2026:

BAE Systems

Cadence Design Systems

General Dynamics

IBM

KYEC

Nokia

Rockwell

Many of our OEM customers use contract manufacturers to assemble their equipment. Accordingly, a significant percentage of our net revenues has been derived from sales to these contract manufacturers. In addition, we sell our products to OEM customers indirectly through domestic and international distributors.

In the case of sales of our products to distributors, the decision to purchase our products is typically made by the OEM customers. In the case of contract manufacturers, OEM customers typically provide a list of approved products to the contract manufacturer, which then has discretion whether or not to purchase our products from that list.

Direct sales to contract manufacturers accounted for 4.9%, 7.9% and 20.5% of our net revenues for fiscal 2026, 2025 and 2024, respectively. Sales to foreign and domestic distributors accounted for 93.3%, 91.7% and 76.3% of our net revenues for fiscal 2026, 2025 and 2024, respectively.

The following direct customers accounted for 10% or more of our net revenues in one or more of the following periods:

Fiscal Year Ended

March 31,

​ ​ ​

2026

​ ​ ​

2025

​ ​ ​

2024

Contract manufacturer:

Flextronics Technology

2.3

%

2.7

%

13.5

%

Distributors:

Avnet Logistics

63.7

49.6

50.6

Holystone

14.2

22.6

2.5

Nexcomm

8.9

9.8

9.3

KYEC was our largest end user customer in fiscal 2026 and 2025. Nokia was our largest end user customer in fiscal 2024. KYEC purchases product through contract manufacturers and distributors. Based on information provided to us by KYEC’s contract manufacturers and distributors, purchases by KYEC represented approximately 14%, 23% and 3% of our net revenues in fiscal 2026, 2025 and 2024, respectively. Nokia purchases products directly from us and through contract manufacturers and distributors. Based on information provided to us by its contract manufacturers and our distributors, purchases by Nokia represented approximately 6%, 12% and 21% of our net revenues in fiscal 2026, 2025 and 2024, respectively. Cadence Design Systems purchases products through contract manufacturers and distributors. Based on information provided to us by its contract manufacturers and our distributors, purchases by Cadence Design Systems represented approximately 12%, 8% and 8% of our net revenues in fiscal 2026, 2025 and 2024, respectively. Our revenues have been substantially impacted by significant fluctuations in sales to Nokia, KYEC and Cadence Design Systems, and we expect that future direct and indirect sales to Nokia, KYEC and Cadence Design Systems will continue to fluctuate substantially on a quarterly basis and that such fluctuations may significantly affect our operating results in future periods. To our knowledge, none of our other OEM customers accounted for more than 10% of our net revenues in fiscal 2026, 2025 or 2024.

Certain of our OEM customers may elect to develop in-house alternatives to the systems they currently build that incorporate our SRAMs, that may use a different memory solution. If an OEM customer makes these changes, that customer could reduce or eliminate its purchases from us. We believe this trend is occurring with Nokia, which

appears to be incorporating internally developed memory solutions into certain of its next-generation products in place of our SRAM products that were included in prior versions of such products. The decline in purchases by Nokia from approximately 21% of our net revenues in fiscal 2024 to approximately 6% in fiscal 2026 may be attributable, in part, to this transition. If other OEM customers similarly choose to develop in-house solutions, our revenues could be further adversely affected.

Sales, Marketing and Technical Support

We sell our products primarily through our worldwide network of independent sales representatives and distributors. As of March 31, 2026, we employed 11 sales and marketing personnel and were supported by over 200 independent sales representatives. We believe these independent sales representatives will enable us to address an expanded customer base with the continuing introduction of our associative computing products in fiscal 2027. We believe that our relationship with our U.S. distributors, Avnet, Mouser and Digi-Key, put us in a strong position to continue to address the Very Fast SRAM memory market in the United States. We currently have regional sales offices located in Hong Kong, Israel and the United States. We believe this international coverage allows us to better serve our distributors and OEM customers by providing them with coordinated support. We believe that our customers’ purchasing decisions are based primarily on product performance, low power consumption, availability, features, quality, reliability, price, manufacturing flexibility and service. Many of our OEM customers have had long-term relationships with us based on our success in meeting these criteria.

Our sales are generally made pursuant to purchase orders received between one and twelve months prior to the scheduled delivery date. Because industry practice allows customers to reschedule or cancel orders on relatively short notice, these orders are not firm and hence we believe that backlog is not a good indicator of our future sales. We typically provide a warranty of up to 36 months on our products. Liability for a stated warranty period is usually limited to replacement of defective products.

Our marketing efforts are, first and foremost, focused on ensuring that the products we develop meet or exceed our customers’ needs. Our marketing efforts are currently focused on marketing our in-place associative computing solutions and our radiation-tolerant and radiation-hardened space grade SRAMs. Previously, those efforts were focused on defining our high-performance SRAM product roadmap. We work closely with key customers to understand their roadmaps and to ensure that the products we develop meet their requirements (primary aspects of which include functionality, performance, electrical interfaces, power, and schedule). Our marketing group also provides technical, strategic and tactical sales support to our direct sales personnel, sales representatives and distributors. This support includes in-depth product presentations, datasheets, application notes, simulation models, sales tools, marketing communications, marketing research, trademark administration and other support functions. We also engage in various marketing activities to increase brand awareness.

We emphasize customer service and technical support in an effort to provide our OEM customers with the knowledge and resources necessary to successfully use our products in their designs. Our customer service organization includes a technical team of applications engineers, technical marketing personnel and, when required, product design engineers. We provide customer support throughout the qualification and sales process and continue providing follow-up service after the sale of our products and on an ongoing basis. In addition, we provide our OEM customers with comprehensive datasheets, application notes and reference designs and access to our FPGA controller IP for use in their product development.

Manufacturing

We outsource our wafer fabrication, assembly and wafer sort testing, which enables us to focus on our design strengths, minimize fixed costs and capital expenditures and gain access to advanced manufacturing technologies.

Our engineers work closely with our outsource partners to increase yields, reduce manufacturing costs, and help assure the quality of our products.

Currently, all of our SRAM and APU wafers are manufactured by TSMC under individually negotiated purchase orders. We do not currently have a long-term supply contract with our foundry, and, therefore, TSMC is not obligated to manufacture products for us for any specified period, in any specified quantity or at any specified price, except as may be provided in a particular purchase order. Our future success depends in part on our ability to secure sufficient capacity at TSMC or other independent foundries to supply us with the wafers we require.

Our APU products are manufactured at TSMC using 28 nanometer and 16 nanometer process technology. The majority of our current SRAM products are manufactured using 0.13 micron, 90 nanometer, 65 nanometer and 40 nanometer process technologies on 300 millimeter wafers at TSMC.

Our master die methodology enables multiple product families, and variations thereof, to be manufactured from a single mask set. As a result, based upon the way available die from a wafer are metalized, wire bonded, packaged and tested, we can create a number of different products. The manufacturing process consists of two phases, the first of which takes approximately thirteen to fifteen weeks and results in wafers that have the potential to yield multiple products within a given product family. After the completion of this phase, the wafers are stored pending customer orders. Once we receive orders for a particular product, we perform the second phase, consisting of final wafer processing, assembly, burn-in and test, which takes approximately eight to ten weeks to complete. Substrates are required in the second phase before the assembly process can begin for many of our products. This two-step manufacturing process enables us to significantly shorten our product lead times, providing flexibility for customization and to increase the availability of our products.

All of our manufactured wafers, including wafers for our APU products, are tested for electrical compliance and most are packaged at Advanced Semiconductor Engineering (“ASE”) which is located in Taiwan. Wistron Neweb Corporation in Taiwan manufactures the boards for our APU product line. Our test procedures require that all of our products be subjected to accelerated burn-in and extensive functional electrical testing which is performed at our Taiwan and U.S. test facilities. Our radiation-hardened products are assembled and tested at Silicon Turnkey Solutions Inc., located near our Sunnyvale, California headquarters facility.

Research and Development

We have devoted substantial resources in the last ten years on the development of our APU products. Our research and development staff includes engineering professionals with extensive experience in the areas of high-speed circuit design, including APU design, as well as SRAM design and systems level networking and telecommunications equipment design. Additionally, we have assembled a team of software development experts in Israel needed for the development of the various levels of software required in the use of our APU products. The design process for our products is complex. As a result, we have made substantial investments in computer-aided design and engineering resources to manage our design process.

Competition

Our existing and potential competitors include many large domestic and international companies, some of which have substantially greater resources, offer other types of memory and/or non-memory technologies and may have longer standing relationships with OEM customers than we do. Unlike us, some of our principal competitors maintain their own semiconductor fabs, which may, at times, provide them with capacity, cost and technical advantages.

Our principal competitors include NVIDIA Corporation and new well-funded entrants for our in-place associative computing solutions and Infineon Technologies AG, Integrated Silicon Solution and Renesas Electronics

Corporation for our SRAM products. We expect additional competitors to enter the associative computing market as well. While some of our competitors offer a broader array of products and offer some of their products at lower prices than we do, we believe that our focus on performance leadership provides us with key competitive advantages.

We believe that our ability to compete successfully in the rapidly evolving markets for “big data” and memory products for the networking and telecommunications markets depends on a number of factors, including:

●product performance, features, including low power consumption, quality, reliability and price;

●manufacturing flexibility, product availability and customer service throughout the lifetime of the product;

●the availability of software tools, such as compilers and libraries that enable customers to easily design products for their specific needs;

●the timing and success of new product introductions by us, our customers and our competitors; and

●our ability to anticipate and conform to new industry standards.

We believe we compete favorably with our competitors based on these factors. However, we may not be able to compete successfully in the future with respect to any of these factors. Our failure to compete successfully in these or other areas could harm our business.

The market for networking memory products is competitive and is characterized by technological change and product obsolescence. Competition could increase in the future from existing competitors and from other companies that may enter our existing or future markets with solutions that may be less costly or provide higher performance or more desirable features than our products. This increased competition may result in price reductions, reduced profit margins and loss of market share.

As our customers’ internal design capabilities evolve, they may choose to create proprietary versions of the networking memory products or other components that they have historically sourced from us and replace our products with these in-house solutions. For example, we believe that Nokia, which has been one of our largest end user customers, is incorporating internally developed alternative memory solutions into certain of its next-generation products in place of the Company’s SRAM products that were included in prior versions of such products. This trend, if it continues or expands to other customers, could result in a reduction in demand for our products and could have a material adverse effect on our business and results of operations.

In addition, we are vulnerable to advances in technology by competitors, including new SRAM architectures as well as new forms of Dynamic Random Access Memory (“DRAM”) and other new memory technologies. Because we have limited experience developing integrated circuit products other than Very Fast SRAMs, any efforts by us to introduce new products based on new technology, including our new in-place associative computing products, may not be successful and, as a result, our business may suffer.

Intellectual Property

Our ability to compete successfully depends, in part, upon our ability to protect our proprietary technology and information. We rely on a combination of patents, copyrights, trademarks, trade secret laws, non-disclosure and other contractual arrangements and technical measures to protect our intellectual property. We believe that it is important to maintain a large patent portfolio to protect our innovations. We currently hold 147 United States patents, including 59 memory patents and 88 associative computing patents, and have in excess of a dozen patent applications pending. We cannot assure you that any patents will be issued as a result of our pending applications. We believe that factors such as the technological and creative skills of our personnel and the success of our ongoing

product development efforts are also important in maintaining our competitive position. We generally enter into confidentiality or license agreements with our employees, distributors, customers and potential customers and limit access to our proprietary information. Our intellectual property rights, if challenged, may not be upheld as valid, may not be adequate to prevent misappropriation of our technology or may not prevent the development of competitive products. Additionally, we may not be able to obtain patents or other intellectual property protection in the future. Furthermore, the laws of certain foreign countries in which our products are or may be developed, manufactured or sold, including various countries in Asia, may not protect our products or intellectual property rights to the same extent as do the laws of the United States and thus make the possibility of piracy of our technology and products more likely in these countries.

The semiconductor industry is characterized by vigorous protection and pursuit of intellectual property rights, which have resulted in significant and often protracted and expensive litigation. We or our foundry from time to time are notified of claims that we may be infringing patents or other intellectual property rights owned by third parties. We have been involved in patent infringement litigation in the past. We have been subject to other intellectual property claims in the past and we may be subject to additional claims and litigation in the future. Litigation by or against us relating to allegations of patent infringement or other intellectual property matters could result in significant expense to us and divert the efforts of our technical and management personnel, whether or not such litigation results in a determination favorable to us. In the event of an adverse result in any such litigation, we could be required to pay substantial damages, cease the manufacture, use and sale of infringing products, expend significant resources to develop non-infringing technology, discontinue the use of certain processes or obtain licenses to the infringing technology. Licenses may not be offered or the terms of any offered licenses may not be acceptable to us. If we fail to obtain a license from a third party for technology used by us, we could incur substantial liabilities and be required to suspend the manufacture of products or the use by our foundry of certain processes.

Government Regulation

We are subject to U.S. export controls and economic sanctions laws and regulations, and certain of our offerings may be classified as dual-use technologies under the Export Administration Regulations or, depending on application, the International Traffic in Arms Regulations. Complying with these regimes may require licenses or other authorizations for specific sales, can delay or prevent transactions, and increases our compliance costs; violations can result in penalties.

Governments in the United States, the European Union and other jurisdictions are developing new and evolving regulations governing artificial intelligence. To the extent applicable to our APU products, particularly in defense, autonomous systems and other sensitive use cases, these frameworks may impose requirements that increase development and compliance costs, delay product deployment, limit certain applications or markets, or require product modifications.

We also perform development under U.S. government-funded agreements. Related data rights, export control classifications and other requirements can affect how and when we commercialize technology developed under such awards and may add administrative complexity to our operations.

Human Capital Resources

As of March 31, 2026, we had 125 full-time employees, including 90 engineers, of which 56 are engaged in research and development and 40 have PhD or MS degrees, 11 employees in sales and marketing, 9 employees in general and administrative capacities and 49 employees in manufacturing. Of these employees, 38 are based in our Sunnyvale facility, 44 are based in our Taiwan facility and 36 are based in our Israel facility. We believe that our future success will depend in large part on our ability to attract and retain highly-skilled, engineering, managerial,

sales and marketing personnel. Our employees are not represented by any collective bargaining unit, and we have never experienced a work stoppage. We believe that our employee relations are good.

Compensation and benefits

Our goal is to attract, motivate and retain talent with a focus on encouraging performance, promoting accountability and adhering to our company values. The future growth and success of our company largely depends on our ability to attract, train and retain qualified professionals. As part of our effort to do so, we strive to offer competitive compensation and benefit programs including a 401(k) Plan, stock options for all employees, flexible spending accounts and paid time off. We understand that effective compensation and benefits programs are important in retaining high-performing and qualified individuals. We continue to assess our healthcare and retirement benefits each year in order to provide competitive benefits to our employees.

Inclusion and belonging

We are committed to our continued efforts to foster an inclusive work environment that supports the global workforce and the communities we serve. We strive to recruit the best people for the job regardless of gender, ethnicity or other protected traits and it is our policy to fully comply with all laws applicable to discrimination in the workplace. Our equity and inclusion principles are also reflected in our employee training and policies. We continue to evaluate our equity and inclusion policies and assess whether enhancements are needed, with guidance from our executive leadership team.

Ethics & Corporate Responsibility

We are committed to ensuring ethical organizational governance, embracing inclusion in the board room and throughout the organization and are committed to observing fair, transparent, and accountable operating practices. We seek to create and foster a healthy, balanced, and ethical work environment for everyone in our organization. To this end, we promote an ethical organizational culture and encourage all employees to raise questions or concerns about actual or potential ethical issues and company policies and to offer suggestions about how we can make our organization better. These practices are set forth in our Code of Business Conduct and Ethics, which is periodically reviewed by all of our employees and is available on our website under “Corporate Governance.”

Health and safety

We are committed to maintaining a safe and healthy workplace for our employees. Our policies and practices are intended to protect our employees.

Investor Information

You can access financial and other information in the Investor Relations section of our website at www.gsitechnology.com. We make available, on our website, free of charge, copies of our annual report on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, and amendments to those reports filed or furnished pursuant to Section 13(a) or 15(d) of the Exchange Act as soon as reasonably practicable after filing such material electronically or otherwise furnishing it to the SEC.

The charters of our Audit Committee, our Compensation Committee, and our Nominating and Governance Committee, our code of conduct (including code of ethics provisions that apply to our principal executive officer, principal financial officer, controller, and senior financial officers) and our corporate governance guidelines are also available at our website under “Corporate Governance.” These items are also available to any stockholder who requests them by calling (408) 331-8800. The contents of our website are not incorporated by reference in this report.

The SEC maintains an Internet site that contains reports, proxy statements and other information regarding issuers that file electronically with the SEC at www.sec.gov.

Information About Our Executive Officers

The following table sets forth certain information concerning our executive officers as of June 1, 2026:

Name

​ ​ ​

Age

​ ​ ​

Title

Lee-Lean Shu

President, Chief Executive Officer and Chairman

Avidan Akerib

Vice President, Associative Computing

Patrick Chuang

Senior Vice President, Memory Design

Didier Lasserre

Vice President, Sales

Douglas Schirle

Chief Financial Officer

Bor-Tay Wu

Vice President, Taiwan Operations

Ping Wu

Vice President, U.S. Operations

Lee-Lean Shu co-founded our company in March 1995 and has served as our President and Chief Executive Officer and as a member of our Board of Directors since inception. Since October 2000, Mr. Shu has also served as Chairman of our Board. From January 1995 to March 1995, Mr. Shu was Director, SRAM Design at Sony Microelectronics Corporation, a semiconductor company and a subsidiary of Sony Corporation, and from July 1990 to January 1995, he was a design manager at Sony Microelectronics Corporation.

Avidan Akerib has served as our Vice President, Associative Computing since MikaMonu Group Ltd. was acquired in November 2015. From July 2011 to November 2015, Dr. Akerib served as co-founder and chief technologist of MikaMonu Group Ltd, a developer of computer in-memory and storage technologies. From July 2008 to March 2011, Dr. Akerib served as chief scientist of ZikBit Ltd., a developer of DRAM computing technologies. From Jan 2001 to July 2007, Dr. Akerib was the General Manager of NeoMagic Israel, a supplier of low-power audio and video integrated circuits for mobile use. Dr. Akerib has a PhD in applied mathematics and computer science from the Weizmann Institute of Science, Israel, and an MSc and BSc in electrical engineering from Tel Aviv University and Ben Gurion University, respectively. Dr. Akerib is the inventor of more than 50 patents related to parallel and In Memory Associative Computing.

Patrick Chuang has served as our Senior Vice President, Memory Design since we acquired substantially all of the assets related to the SRAM memory device product line of Sony Corporation in July 2009. From July 1990 to July 2009, Mr. Chuang served as the Senior Vice President, Memory Design at Sony Microelectronics Corporation, a semiconductor company and a subsidiary of Sony Corporation. From 1980 to 1990, Mr. Chuang served as Design Director of NMOS DRAM at Advanced Micro Devices, a semiconductor manufacturing company.

Didier Lasserre has served as our Vice President, Sales since July 2002. From November 1997 to July 2002, Mr. Lasserre served as our Director of Sales for the Western United States and Europe. From July 1996 to October 1997, Mr. Lasserre was an account manager at Solectron Corporation, a provider of electronics manufacturing services. From June 1988 to July 1996, Mr. Lasserre was a field sales engineer at Cypress Semiconductor Corporation, a semiconductor company.

Douglas Schirle has served as our Chief Financial Officer since August 2000. From June 1999 to August 2000, Mr. Schirle served as our Corporate Controller. From March 1997 to June 1999, Mr. Schirle was the Corporate Controller at Pericom Semiconductor Corporation, a provider of digital and mixed signal integrated circuits. From November 1996 to February 1997, Mr. Schirle was Vice President, Finance for Paradigm Technology, a manufacturer of SRAMs, and from December 1993 to October 1996, he was the Controller for Paradigm Technology. Mr. Schirle was formerly a certified public accountant.

Bor-Tay Wu has served as our Vice President, Taiwan Operations since January 1997. From January 1995 to December 1996, Mr. Wu was a design manager at Atalent, an IC design company in Taiwan.

Ping Wu has served as our Vice President, U.S. Operations since September 2006. He served in the same capacity from February 2004 to April 2006. From April 2006 to August 2006, Mr. Wu was Vice President of Operations at QPixel Technology, a semiconductor company. From July 1999 to January 2004, Mr. Wu served as our Director of Operations. From July 1997 to June 1999, Mr. Wu served as Vice President of Operations at Scan Vision, a semiconductor manufacturer.